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40 minutes ago, Mikorist said:

CMOQ-4HPC ???? Visoki procenat Nikla - OPA bato :hihihihi:

ima se, moze se

Stize jos, a i Onetics, da se proba

:Viannen_loungelizard:

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repost sa big DiyA

no way da prevodim

 

well, really nothing new under the Sun - meaning there is hardly anything specially new or unique that I put here

even if Papa really started us Greedy Boyz playing with Square Law OS arrangements, thing is old as Wheel, in fact

also - using rail series resistors, again Papa's bag of tricks ( for us) but again nothing especially new

neither source follower ( which is introduced here in front of upper output device) used as level shifter is anything new .....

thing is - it's hard to make anything absolutely unique, and wishing just that is right recipe to get yourself in not making anything at all ....... so , studying schematics from everywhere and one can just hope to get in situation to stand on Giant's shoulders 

one day ...... one day ............ 

anyway - here is basic , lets call it , M2 biasing mechanismus;

simple as that:
we have R+ connected to upper part gate,
we have R- connected to lower part gate,
we have some variable impedance connected between gates; varying that impedance we are varying voltage sag across R+ and R- , thus positioning gates at appropriate voltage potential ( one vs. another) , thus setting how much Iq will pass trough output devices

call that variable impedance Rvar, further Mech. , shorted of mechanismus 

cap between gates is there to eliminate AC to appear between gates - we don't want that ........ and also worth to mention - R+ and R- are sorta same in value , difference being just what we need to set output offset to 0 ( N gate and P gate voltages not exactly being identical)

 

M2-biasing-principle.png

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M2 in more details;

as said - it's relatively easy when we want to use source resistors as Iq reference points; I mean - easy when we got recipe from Mithrandir

also easy when we are using lower and upper output parts having so-so equal gate voltages, opposite side of output node, meaning +4V and -4V

optodiode connected across source resistors, series resistor to optodiode taking care that diode is not getting more than nominally 1V1 , at preferred Iq through source resistors

opto transisttor is now MECH. , governing current through R+ and R- , everything is Wine and Roses

M2-more-details.png

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things are getting tricky when we want to use different part than Mosfet ( either up or down) , while using same biasing technique

say SissySIT (DEFiSIT) - Toking Bigun is different to N mosfet in that way that gate voltage is opposite in sign (differene between enhanced vs. depletion mode parts, +4V-ish vs. -3V-ish)

now voltage window between gates is no more twice 4v (+4V reaching down to -4V), now it is -3Vsomething reaching to -4V

we are happy campers if we have SIT with Ugs no greater in number than, say , 3V7 , so we have big enaough voltage window between gates, to squeeze optotransistor in

some P mosfets are having Ugs in range of -4V5, thus allowing as little broader batch of Tokins to be used, but that's just one more thing to take care with, endless parts picking .......

current through R+ and R- is, logically, one current; due to fact that gates are not symmetrical to output node, now R+ and R- can't be approx. same in value, resulting in few problems, of which most important one is that mains fluctuation resulting in sliding output DC offset , also parts TempCo playing game with Iq, then rails fluctuating down ( if not regged) etc.

Luckily , I succeeded more or less in set of compromises while making SissySIT , both first one and R.2

Bummer.png

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now, how to solve those issues ...... unequal Rail resistors , SIT parts with greater Ugs number ..... sometimes time is needed either to make space for new problems in thick skull, or just to have some leeway, then be able to step aside and look at problem from another point

level shifter part, that's it

small mosfet, so Ugs is sorta symmetric to big mosfet down Ugs, .... suddenly Rail resistors are sorta equal again, practically no gate currents to complicate things ( as is case with some not so well behaving Tokins)

principal schm down; ignore MECH. principle fro now

I think everything is clear, except note about LS resistor - its value is roughly SIT Ugs divided with current trough small Mosf/LS res./CCS ;say that you put value just being in ballpark; you can always go back and alter its value , to get wanted symmetry of lower and upper mosfet Ugs values

Eureka.png

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